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HSP43168
Data Sheet July 27, 2009 FN2808.12
Dual FIR Filter
The HSP43168 Dual FIR Filter consists of two independent 8-tap FIR filters. Each filter supports decimation from 1 to 16 and provides on-board storage for 32 sets of coefficients. The Block Diagram shows two FIR cells each fed by a separate coefficient bank and one of two separate inputs. The outputs of the FIR cells are either summed or multiplexed by the MUX/Adder. The compute power in the FIR Cells can be configured to provide quadrature filtering, complex filtering, 2-D convolution, 1-D/2-D correlations, and interpolating/decimating filters. The FIR cells take advantage of symmetry in FIR coefficients by pre-adding data samples prior to multiplication. This allows an 8-tap FIR to be implemented using only 4 multipliers per filter cell. These cells can be configured as either a single 16-tap FIR filter or dual 8-tap FIR filters. Asymmetric filtering is also supported. Decimation of up to 16 is provided to boost the effective number of filter taps from 2 to 16 times. Further, the Decimation Registers provide the delay necessary for fractional data conversion and 2-D filtering with kernels to 16x16. The flexibility of the Dual is further enhanced by 32 sets of user programmable coefficients. Coefficient selection may be changed asynchronously from clock to clock. The ability to toggle between coefficient sets further simplifies applications such as polyphase or adaptive filtering. The HSP43168 is a low power fully static design implemented in an advanced CMOS process. The configuration of the device is controlled through a standard microprocessor interface.
Features
* Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR * 10-Bit Data and Coefficients * On-Board Storage for 32 Programmable Coefficient Sets * Up To: 256 FIR Taps, 16x16 2-D Kernels, or 10x19-Bit Data and Coefficients * Programmable Decimation to 16 * Programmable Rounding on Output * Standard Microprocessor Interface * Pb-Free Available (RoHS Compliant)
Applications
* Quadrature, Complex Filtering * Image Processing * Polyphase Filtering * Adaptive Filtering
Ordering Information
PART NUMBER HSP43168VC-45 HSP43168VC-45Z (Note) HSP43168JC-33 HSP43168JC-33Z (Note) PART MARKING HSP43168VC-45 HSP43168VC-45Z HSP43168JC-33 HSP43168JC-33Z TEMP. RANGE (C) 0 to +70 0 to +70 0 to +70 0 to +70 PACKAGE 100 Ld MQFP 100 Ld MQFP (Pb-free) 84 Ld PLCC 84 Ld PLCC PKG. DWG. # Q100.14x20 Q100.14x20 N84.1.15 N84.1.15
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2001, 2004, 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HSP43168 Block Diagram
CIN0 - 9 A0 - 8 WR CSEL0 - 4 10 9 CONTROL/ CONFIGURATION
COEFFICIENT BANK A 10 INA0 - 9 FIR CELL A MUX MUX / ADDER 9 OEL OEH MUX
COEFFICIENT BANK B
FIR CELL B
INB0 - 9/ OUT0 - 8
10
19
OUT9 - 27
Pinouts
HSP43168 (84 LD PLCC) TOP VIEW
CIN 9 CSEL 4 CSEL 3 CSEL 2 CSEL 1 CSEL 0 VCC A8 A7 A6 A5 A4 A3 A2 A1 A0 GND WR MUX 1 MUX 0 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 INB 8 INB 7 INB 6 INB 5 GND INB 4 INB 3 INB 2 INB 1 INB 0 OEL OUT 9 OUT 10 VCC OUT 11 OUT 12 OUT 13 OUT 14 OUT 15 OUT 16 GND CIN 8
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 CIN 7 CIN 6 CIN 5 CIN 4 GND CIN 3 CIN 2 CIN 1 CIN 0 INA 9 INA 8 INA 7 INA 6 INA 5 VCC INA 4 INA 3 INA 2 INA 1 INA 0 INB 9 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RVRS FWD SHFTEN TXFR ACCEN VCC CLK GND OEH OUT 27 OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 18 OUT 17 VCC
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HSP43168 Pinouts
(Continued) HSP43168 (100 LD MQFP) TOP VIEW
CIN9 CSEL4 CSEL3 CSEL2 CSEL1 CSEL0 VCC VCC A8 A7 A6 A5 A4 A3 A2 A1 A0 GND GND WR 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CIN8 NC CIN7 NC CIN6 CIN5 CIN4 GND GND CIN3 CIN2 CIN1 CIN0 INA9 INA8 INA7 INA6 INA5 VCC VCC INA4 INA3 INA2 INA1 INA0 NC NC INB9 INB8 INB7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 INB6 INB5 GND GND INB4 INB3 INB2 INB1 INB0 OEL OUT9 OUT10 VCC VCC OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 MUX1 MUX0 RVRS NC FWRD SHIFTEN TXFR ACCEN VCC VCC CLK GND GND OEH OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 NC VCC VCC GND GND
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HSP43168 Pin Description
SYMBOL VCC GND CIN0-9 A0-8 I I TYPE VCC: +5V power supply pin Ground Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the LSB Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on the rising edge of WR Coefficient Select. This input determines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. Input to FIR A. INA0 is the LSB Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the output bus, and INB9 is the MSB of these bits. 19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 is the MSB. Shift Enable. This active low input enables clocking of data into the part and shifting of data through the Decimation Registers. Forward ALU Input Enable. When active low, data from the forward decimation path is input to the ALUs through the "a" input. When high, the "a" inputs to the ALUs are zeroed. Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through the "b" input. When high, the "b" inputs to the ALUs are zeroed. Data Transfer Control. This active low input switches the LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various configurations. Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables (OEL, OEH) are registered by the rising edge of CLK. Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low. Output Enable High. This three-state control enables OUT9-27 when OEH is low. Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the Accumulator. No connect DESCRIPTION
WR CSEL0-4
I I
INA0-9 INB0-9
I I/O
OUT9-27
O
SHFTEN
I
FWRD FWD RVRS
I
I
TXFR
I
MUX0-1
I
CLK
I
OEL OEH ACCEN
I I I
NC
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1 TXFR DELAY 4 0 DELAY 3 FIR A REVERSE PATH M U X
DATA REVERSAL ENABLE
DATA FEEDBACK CIRCUITRY
1 DELAY 4 DELAY 3 0 M U X
FIR A ODD/EVEN # TAPS
DECIMATION REGISTERS M U X
LIFO A LIFO B DELAY 1-16 D EM MU UX X
ODD/EVEN SYMMETRY MODE SELECT
FIR B ODD/EVEN # TAPS
DECIMATION REGISTERS M U X
DATA FEEDBACK CIRCUITRY LIFO A LIFO B DELAY 1-16 D EM MU UX X
ODD/EVEN
NUMBER OF TAPS
FIR A FORWARD PATH
DELAY 1-16
DELAY 1-16
DELAY 1-16
DELAY 1-16
DELAY 1-16
DELAY 1-16
SHFTEN
DELAY 3
DATA REVERSAL ENABLE
INA0-9 10 M U X DELAY 3 DELAY 3 10 10 A B ALU A B ALU A B ALU DELAY 1-16 DELAY 1-16 DELAY 1-16 DELAY 1-16 M U X DELAY 1-16 DELAY 1-16 DELAY 1-16 FIR B REVERSE PATH FIR B FORWARD PATH
5
INB0 INB1-9/ OUT0-8 FWRD RVRS CSEL0-4 CLK ACCEN MUX0-1 CIN0-9 A0-8 WR
9
ODD/EVEN
SYMMETRY A B ALU A B ALU A B ALU A B ALU
ODD/EVEN
SYMMETRY
A B ALU DELAY 3 11 DELAY 3 REG
FIR B INPUT
SOURCE
REG
REG
REG
MODE SELECT
REG
REG
REG
REG
HSP43168
11
X
10 5 DELAY 4 21 REG
COEF BANK 0
X
COEF BANK 1
X
COEF BANK 2
X
COEF BANK 3
X
COEF BANK 0
X
COEF BANK 1
X
COEF BANK 2
X
COEF BANK 3
REG
REG
REG
REG
REG
REG
REG
FIR A ACCUMULATOR 0 M U X R E G 0 ADDER 22 OUTPUT HOLDING REGISTER
FIR B ACCUMULATOR M U X R E G
ADDER
REG DELAY 5
FIR CELL A
REG
OUTPUT HOLDING REGISTER
FIR CELL B
2 DELAY 6 10 9 CONTROL
MODE SELECT ODD EVEN SYMMETRY FIR A ODD/EVEN # TAPS FIR B ODD/EVEN # TAPS FIR B INPUT SOURCE DATA REVERSAL ENABLE ROUND ENABLE DECIMATION FACTOR
MUX/ ADDER 28 DELAY 2
ROUND ENABLE
9
19 OUT9-27
FN2808.12 July 27, 2009
OEL OEH
Processor control words Decimation factor
FIGURE 1. DUAL FIR FILTER
HSP43168 Functional Description
As shown in Figure 1, the HSP43168 consists of two 4-multiplier FIR filter cells which process 10-bit data and coefficients. The FIR cells can operate as two independent 8-tap FIR filters or two 4-tap asymmetric filters at maximum I/O rates. A single filter mode is provided which allows the FIR cells to operate as one 16-tap FIR filter or one 8-tap asymmetric filter. On board coefficient storage for up to 32 sets of 8 coefficients is provided. The coefficient sets are user selectable and are programmed through a microprocessor interface. Programmable decimation to 16 is also provided. By utilizing Decimation Registers together with the coefficient sets, polyphase filters are realizable which allow the user to trade data rate for filter taps. The MUX/Adder can be configured to either add or multiplex the outputs of the filter cells depending upon whether the cells are operating in single or dual filter mode. In addition, a shifter in the MUX/Adder is provided for implementation of filters with 10-bit data and 20-bit coefficients or vice versa. The Dual FIR Filter has a "pipeline" delay of 8 CLK periods, once normal filtering operations begin. Five typical filtering operation examples are provided in "Application Examples" on page 10 as a guide to configuration and control of the Dual FIR Filter. During normal filter operations, the location and duration of the TXFR signal assertions are determined by the filter configuration and operation mode. Once set, these signal parameters must be maintained during normal operation to ensure proper data alignment in the part. Once the part is reset, do not change TXFR unless you load the configuration again. Note: The fixed or periodic relationship between the TXFR signal and CLK must be maintained for valid filter operation. This relationship can only change when CLK is halted and new configuration control words are loaded into the device.
Microprocessor Interface
The Dual FIR has a 20 pin write only microprocessor interface for loading data into the Control Block and Coefficient Banks. The interface consists of a 10-bit data bus (CIN0-9), a 9-bit address bus (A0-8), and a write input (WR) to latch the data into the on-board registers on a rising edge. The configuration control and coefficient data loading is asynchronous to CLK.
Preparing the Dual FIR for Operation
Two configuration steps are required to prepare the Dual FIR Filter for normal operation: 1) loading the Configuration Control Registers, and 2) loading the FIR Filter Coefficients. Configuration Control Registers are loaded by placing the control register address on address lines A0-8, placing the configuration data on the configuration input lines CIN0-9, and asserting the WR line (followed by a release of the assertion). This action creates a rising edge on the WR line, which clocks the address and configuration data into the part. The details of the "Load Configuration" process are outlined in "Microprocessor Interface" on page 6. FIR Coefficients are loaded by placing the address of the Coefficient Data Bank on the address lines A0-8, placing the FIR 10-bit coefficient values on the configuration input lines CIN0-9 and then asserting the WR line (followed by a release of the assertion). This action creates a rising edge on the WR line, which clocks the FIR Coefficient Band address and FIR Coefficient data into the part. The details of the "Load FIR Coefficient" process are outlined in "Coefficient Bank" on page 8. Both the Configuration Load and FIR Coefficient Load can be done as a sequence of asynchronous write commands to the Dual FIR Filter. Once these actions are complete, the part is ready for normal filter operation. The CLK, TXFR, FWRD, RVRS, ACCEN, and SHFTEN signals must be asserted in a manner determined by the application. MUX0-1 must meet the setup and hold times with respect to clock for proper filter operation. Details of the MUX1-0 control can be found in "Output MUX/Adder" on page 9. Details of the ACCEN control can be found in "FIR Cell Accumulator" on page 9. Bit locations for the various filter control/configuration signals can be found in "Input/Output Formats" on page 10. 6
Control Block
The Dual FIR is configured by writing to the registers within the Control Block. Figure 2 shows the timing diagram for writing to the Configuration Control Registers. These Control Registers are memory mapped to Address 000H (H = Hexadecimal) and 001H on A0-8. The Filter Coefficient Registers are mapped to 1XXH (X = value described in "Coefficient Bank" on page 8).
RESET
WR A8-0 000H
001H
C9-0
FIGURE 2. LATCHING C9-0 VALUES INTO ADDRESS A8-0 REGISTERS
The format of the Control Registers is shown in Table 1 and Table 2. Writing to any of the Control/Configuration Registers causes a reset which lasts for 6 CLK cycles following the assertion of WR. The reset caused by Writing Registers in the Control Block will not clear the contents of the Coefficient Bank. As shown in Figure 2, either Configuration Control Register can be written to during reset.
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HSP43168
TABLE 1. CONFIGURATION/CONTROL WORD 0 BIT DEFINITIONS CONTROL ADDRESS 000H BITS 3-0 FUNCTION DESCRIPTION Decimation Factor (N) R = N + 1 0000 = No Decimation. 1111 = Decimation by 16. Mode Select 0 = Single Filter Mode. 1 = Dual Filter Mode. (also 20-Bit Coefficient Filter) 0 = Even Symmetric Coefficients. 1 = Odd Symmetric Coefficients. 0 = Odd Number of Taps in Filter. 1 = Even Number of Taps in Filter. (Defined Same as FIR A Above). 0 = Input from INA0-9. 1 = Input from INB0-9. Set to 0 for Proper Operation.
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(see Figure 1). Coefficient symmetry is selected by bit 5. Bits 6 and 7 are programmed to configure the FIR cells for odd or even filter lengths (number of taps). Bit 8 selects the FIR B input source when the FIR cells are configured for independent operation. Bit 9 must be programmed to 0. Note: When the filter is programmed for even-taps, the TXFR signal is delayed by only three CLKS (see Figure 1). For odd-taps, the TXFR signal is delayed by four CLKS. The 4 LSBs of the control word loaded at address 001H are used to configure the format of the FIR cell's data and coefficients. Bit 4 is programmed to enable or disable the reversal of data sample order prior to entering the Reverse Path Decimation Registers. Data reversal is required for symmetric filter coefficient sets of both even or odd numbers of filter taps. Asymmetric filters and some decimated symmetric filters require the data reversal to be off. Bits 5 to 9 are used to support programmable rounding on the output.
5 6 7 8 9
Odd/Even Filter Coefficient Symmetry FIR A Odd/Even Number of Taps FIR B Odd/Even Number of Taps FIR B Input Source Not Used
FIR Filter Cells
Each FIR filter cell is based on an array of four 11x10-bit two's complement multipliers. One input of the multipliers comes from the ALU's which combine data shifting through the Forward and Reverse Decimation Registers. The second multiplier input comes from the user programmable coefficient bank. The multiplier outputs are fed to an accumulator whose result is passed to the output section where it is multiplexed or added with the result from the other FIR cell.
TABLE 2. CONFIGURATION/CONTROL WORD 1 BIT DEFINITIONS CONTROL ADDRESS 001H BITS 0 1 2 3 4 8-5 FUNCTION FIR A Input Format FIR A Coefficient Format FIR B Input Format FIR B Coefficient Data Reversal Enable Round Position DESCRIPTION 0 = Unsigned. 1 = Two's Complement. (Defined same as FIR A input). (Defined same as FIR A input). (Defined same as FIR A input). 0 = Enabled. 1 = Disabled. 0000 = 2-10. 1011 = 21. (See Figure 4) 0 = Enabled. 1 = Disabled.
Decimation Registers
The Forward and Reverse Decimation Shift Registers can be configured for decimation factors from 1 to 16 (see Table 1, bits 0-3). Note: Setting the decimation factor only affects the Delay Registers between filter taps, not the filter control multiplexers. Example 4 and Example 5 in "Application Examples" on page 10 discuss how to configure the part for actual decimation applications. The Reverse Shifting Registers with the data reversal logic are used to take advantage of symmetry in linear phase filters by aligning data at the ALUs for pre-addition prior to multiplication by the common coefficient. When the FIR cells are configured in single filter mode, the Decimation Registers in FIR cell A and FIR cell B are cascaded. This extended filter tap delay path allows computation of a filter which is twice the size of that capable using a single cell. The Decimation Registers also provide data storage for polyphase or 2-D filtering applications (See "Application Examples" on page 10). The Data Feedback Circuitry in each FIR cell is responsible for transferring data from the Forward to the Reverse Shifting Decimation Registers. This circuitry feeds blocks of samples into the reverse shifting decimation path in either reversed or non-reversed sample order. The MUX/DEMUX structure at the input to the Feedback Circuitry routes data to the LIFOs or the delay stage depending on the selected
9 NOTES:
Round Enable
1. Address locations 002H to 011H are reserved, and writing to these locations will have unpredictable effects on part configuration.
The 4 LSBs of the control word loaded at address 000H are used to select the decimation factor. The Decimation Factor is programmed to one less than the number of delays between filter taps as shown in Equation 1.
DF = ( CLK delays between taps ) - 1 (EQ. 1)
For example, if the 4 LSBs are programmed with a value of 0010, the Forward and Reverse Shifting Decimation Registers are each configured with a delay of 3. Bit 4 is used to select whether the FIR cells operate as two independent filters or one extended length filter. Dual filter mode assumes Filter A and Filter B are separate independent filters. In the single filter mode, the data is routed through the forward paths of Filters A and B before entering the reverse paths of Filters A and B
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HSP43168
configuration. The MUX on the Feedback Circuitry Output selects which storage element feeds the Reverse Shifting Decimation Registers. In applications requiring reversal of sample order, the FIR cells are configured with data reversal enabled (see Table 2, CW5, bit 4 = 0). In this mode, data is transferred from the forward to the backward Shifting Registers through a pingponged LIFO structure. While one LIFO is being read into the backward shifting path, the other LIFO is written with data samples. The MUX/DEMUX controls which LIFO is being written, and the MUX on the Feedback Circuitry output controls which LIFO is being read. A low on TXFR and SHIFTEN, switches the LIFOs being read and written, which causes the block of data to be read from the structure in reversed in sample order (See Example 4 in "Application Examples" on page 10). The frequency with which TXFR is asserted determines size of the data blocks in which sample order is reversed. For example, if TXFR is asserted once every three CLKs, blocks of 3 data samples with order reversed, would be fed into the Backward Decimation Registers. Note: Altering the frequency or phase of TXFR assertion once a filtering operation has begun will invalidate the filtering result. In applications which do not require sample order reversal, the FIR cells must be configured with data reversal disabled (see Table 2, CW5, Bit 4 = 1). In addition, TXFR must be asserted to ensure proper data flow. In this configuration, data to the backward shifting decimation path is routed though a delay stage instead of the pingpong LIFOs. The number of registers in the delay stage is based on the programmed decimation factor. Note: Data reversal must be disabled and TXFR must be asserted for filtering applications which do not use decimation. The shifting of data through the Forward and Reverse Decimation Registers is enabled by asserting the SHFTEN input. When SHFTEN is high, data shifting is disabled, and the data sample latched into the part on the previous clock is the last input to the filter structure. The data sample at the filter input when SHFTEN is asserted, will be the next data sample into the forward decimation path. When operating the FIR cells as two independent filters, FIR A receives input data via INA0-9 and FIR B receives data from either INA0-9 or INB0-9 depending on the application (see Table 1). When the FIR cells are configured as a single extended length filter, the forward and reverse decimation paths of the two FIR cells are cascaded. In this mode, data is transferred from the forward decimation path to the reverse decimation path by the Data Feedback Circuitry in FIR B. Thus, the manner in which data is read into the reverse decimation path is determined by FIR B's configuration. When the decimation paths are cascaded, data is routed through the fourth delay stage in FIR A's forward path to FIR B. 8 The configuration of the FIR cells as even or odd length filters determines the point in the forward decimation path from which data is multiplexed to the Data Feedback Circuitry. For example, if the FIR cell is configured as an odd length filter, data prior to the last register in the third forward decimation stage is routed to the Feedback Circuitry. If the FIR cell is configured as an even length filter, data output from the third forward decimation stage is multiplexed to the Feedback Circuitry. This is required to ensure proper data alignment with symmetric filter coefficients (See "Application Examples" on page 10).
ALUs
Data shifting through the forward and reverse decimation paths feed the "a" and "b" inputs of the ALUs respectively. The ALUs perform an "b+a" operation if the FIR cell is configured for even symmetric coefficients or an "b-a" operation if configured for odd symmetric coefficients. Control Word 0, Bit 5 is used to set the ALU operation. For applications in which a pre-add or subtract is not required, the "a" or "b" input can be zeroed by disabling FWRD or RVRS respectively. This has the effect of producing an ALU output which is either "a", "-a", or "b" depending on the filter symmetry chosen. For example, if the FIR cell is configured for an even symmetric filter with FWRD low and RVRS high, the data shifting through the Forward Decimation Registers would appear on the ALU output. Table 3 details the ALU configurations, where "a" is the ALU data input from the front decimation delay registers and "b" is the ALU data from the back decimation delay registers.
TABLE 3. ALU CONFIGURATIONS ALU OUT a+b +b +a b-a +b -a SYMMETRY FWD RVS 0 (Even) 0 (Even) 0 (Even) 0 (Even) 1 (Odd) 1 (Odd) 1 (Odd) 1 (Odd) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 DESCRIPTION Even Number of Taps, Even Symmetry (Example 1) Even Symmetry Even Symmetry Even Symmetry Even Number of Taps, Odd Symmetry (Example 2) Odd Symmetry Odd Symmetry Odd Symmetry
Coefficient Bank
The output of the ALU is multiplied by a coefficient from one of 32 user programmable coefficient sets. Each set consists of 8 coefficients (4 coefficients for FIR A and 4 for FIR B). CSEL0-4 is used to select a coefficient set to be used. Coefficient sets may be switched every clock to support polyphase filtering operations.
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HSP43168
The coefficients are loaded into On-Board Registers using the microprocessor interface, CIN0-9, A0-8, and WR. Each multiplier within the FIR Cells is driven by a coefficient bank with one of 32 coefficients. These coefficients are addressed as shown in Table 4. The inputs A0-1 specify the Coefficient Bank for one of the four multipliers in each FIR Cell; A2 specifies FIR Cell A or B; Bits A7-3 specify one of 32 sets in which the coefficient is to be stored. For example, an address of 10dH would access the coefficient for the second multiplier in FIR B in the second coefficient set.
TABLE 4. FIR COEFFICIENT WRITE ADDRESSES FIR COEFF. A8 1 1 1 1 1 1 1 1 CSEL (4-0) COEFF. SET A7-3 xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x CELL A/B A2 0 0 0 0 1 1 1 1
Output MUX/Adder
The contents of each FIR Cell's Output Holding Register is summed or multiplexed in the Mux/Adder. The operation of the Mux/Adder is controlled by the MUX1-0 inputs as shown in Table 5. Applications requiring 10-bit data and 20-bit coefficients or 20-bit data and 10-bit coefficients are made possible by configuring the MUX/Adder to scale FIR B's output by 2-10 prior to summing with FIR A. When the Dual FIR is configured as two independent filters, the MUX1-0 inputs would be used to multiplex the filter outputs of each cell. For applications in which FIR A and B are configured as a single filter, the MUX/Adder is configured to sum the output of each FIR cell.
NOTE: While a 20-bit coefficient filter is a single filter, the mode select is set to 1 and MUX1-0 is set to 00. TABLE 5. MUX1-0 BIT DEFINITIONS MUX1-0 DECODING MUX1-0 00 01 10 11 OUT0-27 FIRA + FIRB (FIR B Scaled by 2-10) FIRA + FIRB FIRA FIRB
MULTIPLIER A1-0 00 01 10 11 00 01 10 11
DESTINATION FIR A A A A B B B B BANK 0 1 2 3 0 1 2 3
FIR Cell Accumulator
The registered outputs from the multipliers in each FIR cell feed an accumulator. The ACCEN input controls each accumulator's running sum and the latching of data from the accumulator into the Output Holding Registers. When ACCEN is low, feedback from the accumulator adder is zeroed which disables accumulation. Also, output from the accumulator is latched into the Output Holding Registers. When ACCEN is asserted, accumulation is enabled and the contents of the Output Holding Registers remain unchanged.
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HSP43168 Input/Output Formats
The Dual FIR supports mixed mode arithmetic with both unsigned and two's complement data and coefficients. The input and output formats for both data types are shown in Figure 3. If the Dual FIR is configured as an even symmetric filter with unsigned data and coefficients, the output will be unsigned. Otherwise, the output will be two's complement. The MUX/Adder can be configured to implement programmable rounding at bit locations 2-10 through 21. The round is implemented by adding a 1 to the specified location (see Table 2). Figure 4 illustrates the rounding operation. For example, to configure the part such that the output is rounded to the 10 MSBs, OUT18 - 27, the round position would be chosen to be 2-1. The negative sign on the MSB indicates 2's complement format.
INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL TWO'S COMPLEMENT 9 -20 8 .2-1 7 2-2 6 2-3 5 2-4 4 2-5 3 2-6 2 2-7 1 2-8 0 2-9
27 26 25 24 23 22 21 20 19 IOUT 18 9-27 17 16 15 14 13 12 11 10 9 8 7 6 5 IOUT 4 0-8 3 2 1 0
21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10
8 9 10 11 12 13 14 15 16 17 18 19
1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 "ROUND POSITION" VALUE
NUMBER OF OUTPUT BITS LOCATION OF ADDITION OF 1 OUTPUT BITS
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL TWO'S COMPLEMENT 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 -29 28 27 26 25 24 23 22 21 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL TWO'S COMPLEMENT 8 2-10 7 2-11 6 2-12 5 2-13 4 2-14 3 2-15 2 2-16 1 2-17 0 2-18
FIGURE 4. ROUND POSITION BIT DEFINITION
Application Examples
In this section a number of examples are presented which detail even, odd, symmetric, asymmetric, decimating and dual FIR filter configurations. These examples are intended to illustrate the different operational features of the HSP43168 and should be used as a guide in developing an application specific filter configuration. Use Table 6 to select and find the example that best matches your application.
TABLE 6. FILTER EXAMPLE SELECTION GUIDE
INPUT DATA FORMAT INA0-9, INB0-9 FRACTIONAL UNSIGNED 9 20 8 .2-1 7 2-2 6 2-3 5 2-4 4 2-5 3 2-6 2 2-7 1 2-8 0 2-9
FILTER TYPE Even Tap Even Symmetric Odd Tap Even Symmetric
EXAMPLE NUMBER 1 2 3 4 5 6
OUTPUT DATA FORMAT OUT9-27 FRACTIONAL UNSIGNED 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 29 28 27 26 25 24 23 22 21 20 .2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 OUTPUT DATA FORMAT OUT0-8 FRACTIONAL UNSIGNED 8 2-10 7 2-11 6 2-12 5 2-13 4 2-14 3 2-15 2 2-16 1 2-17 0 2-18
Asymmetric Even Tap Decimating Odd Tap Decimating Dual Decimating
FIGURE 3. INPUT/OUTPUT FORMAT DEFINITIONS
Examples 1 through 5 are explained using a single four tap FIR cell, but the same concept applies to FIR filters which use both FIR cells (A and B) in a single filter configuration. Example 6 details a dual filter mode where FIR cell A and B implement different digital filters. All examples are functionally verified configurations. Each example details a complete design solution, including a block diagram, a data/coefficient alignment illustration, a data flow diagram and a control signal timing diagram.
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Two programmable Configuration Control Registers define a unique FIR filter configuration. Register 000H has all filter configuration unique parameters, while Register 001H, Bit 4, is filter configuration unique. Table 7 details the configuration control register values, the number of filter coefficient banks required and the MUX1-0 control values for each filter example.
TABLE 7. CONFIGURATION CONTROL REGISTER VALUES REG 000 HEX 1d0 110 110 1dN 11N 15N or 19N REG # OF FILTER 001 COEFFICIENT BANKS HEX 010 010 010 000 000 000 Bit 4 1 1 2 N+1 N+1 N+1 MUX 1-0 10
X9 X8 X7 X6 X5 X4 X3 X2 X1 X0
Figure 7A shows the data sample alignment at the preadders for the data/coefficient alignment shown in Figure 6.
C3 C2 h(n) C0 C1 C3 C2 C1 C0 8 TAPS
FILTER TYPE Even Tap Even Symmetric Odd Tap Even Symmetric Asymmetric Even Tap Decimate by N+1 Odd Tap Decimate by N+1 Dual: Even and Odd Tap Decimate by N+1
x(n)
10 10 10 10 10 and 11 FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP EVEN SYMMETRIC FILTER
The dual filter application is configured by writing 1d0H to address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Since this application does not use decimation, the 4th bit of the Control Register at Address 001H must be set to disable data reversal (see Table 2). Failure to disable data reversal will produce erroneous results. Using this architecture, only the unique coefficients need to be stored in the Coefficient Bank. For example, the above filter would be stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to Address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. To operate the HSP43168 in this mode, TXFR is tied low to ensure proper data flow; both FWRD and RVRS are tied low to enable data samples from the forward and reverse data paths to the ALUs for pre-adding; ACCEN is tied low to prevent accumulation over multiple CLKs; SHFTEN is tied low to allow shifting of data through the Decimation Registers; MUX0-1 is programmed to multiplex the output the of either FIR A or FIR B; CSEL0-4 is programmable to access the stored coefficient set, in this example CSEL = 00000.
Example 1: Even-Tap Even Symmetric Filter Example
The HSP43168 may be configured as two independent 8-tap symmetric filters as shown by the Block Diagram in Figure 5. Each of the FIR cells takes advantage of symmetric filter coefficients by pre-adding data samples common to a given coefficient. As a result, each FIR cell can implement an 8-tap symmetric filter using only four multipliers. Similarly, when the HSP43168 is configured in single filter mode a 16-tap symmetric filter is possible by using the multipliers in both cells.
HSP43168 8-TAP EVEN SYMMETRIC INA0-9 A A 8-TAP EVEN SYMMETRIC B B INB0-9 FIR B FIR A M U X OUT9-27
0
1
2
3
FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS
The operation of the FIR cell is better understood by comparing the data and coefficient alignment for a given filter output, Figure 6, with the data flow through the FIR cell, as shown in Figure 7. The Block Diagrams in Figure 7 are a simplification of the FIR cell shown in Figure 1. For simplicity, the ALUs and FIR Cell Accumulators were replaced by adders, and the Pipeline Delay Registers were omitted. In this example, we will only show the data flow through one of the two FIR cells. In Figure 7, the order of the data samples within the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is given by the equation at the bottom of each block diagram.
7
6
5
4
+
C0 C1
+
C2
+
C3
+
+
(X7 + X0)C0 + (X6 + X1)C1 + (X5 + X2)C2 + (X4 + X3)C3
FIGURE 7A. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED-FORWARD STAGE
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1 2 3 4
8
7
6
5
The operation of the FIR cell for odd length filters is better understood by comparing the data/coefficient alignment in Figure 9 with the Data Flow Diagrams in Figure 10. The Block Diagrams in Figure 10 are a simplification of the FIR cell shown in Figure 1.
C3 C2 C2 C1 C0 h(n) C0 C1 7-TAPS
+
C0 C1
+
C2
+
C3
+
+
(X8 + X1)C0 + (X7 + X2)C1 + (X6+X3)C2 + (X5 + X4)C3 x(n)
FIGURE 7B. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED-FORWARD STAGE
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
2
3
4
5
FIGURE 9. DATA/COEFFICIENT ALIGNMENT FOR 7-TAP SYMMETRIC FILTER
9
8
7
6
+
C0 C1
+
C2
+
C3
+
For odd length filters, proper data/coefficient alignment is ensured by routing data entering the last register in the third forward decimation stage to the Backward Shifting Registers. In this configuration, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from both the Forward and Backward Shifting Registers.
0 1 2 3
+
(X9 + X2)C0 + (X8 + X3)C1 + (X7 + X4)C2 + (X6 + X5)C3
FIGURE 7C. DATA FLOW AS DATA SAMPLE 9 IS CLOCKED INTO THE FEED-FORWARD STAGE FIGURE 7. DATA FLOW DIAGRAMS FOR 8-TAP SYMMETRIC FILTER
6
5
4
3
+
C0 C1
+
C2
+
C3/2
+
Example 2: Odd-Tap Even Symmetric Filter Example
The HSP43168 may be configured as two independent 7-tap symmetric filters with a Functional Block Diagram shown in Figure 8. Again, this example shows data flow through one of the two FIR cells. As in the 8-tap filter example, the HSP43168 implements the filtering operation by summing data samples sharing a common coefficient prior to multiplication by that coefficient. However, for odd length filters the pre-addition requires that the center coefficient be scaled by 1/2.
+
(X6 + X0)C0 + (X5 + X1)C1 + (X4 + X2)C2 + (X3 + X3)C3/2
FIGURE 10A. DATA FLOW AS DATA SAMPLE 6 IS CLOCKED INTO THE FEED-FORWARD STAGE
1
2
3
4
7
6
5
4
+
HSP43168 7-TAP EVEN SYMMETRIC INA0-9 A A 7-TAP EVEN SYMMETRIC B B INB0-9 FIR B FIR A M U X OUT9-27 C0 C1
+
C2
+
C3/2
+
+
(X7 + X1)C0 + (X 6 + X2)C1 + (X5 + X3)C2 + (X4 + X4)C3/2
FIGURE 8. USING HSP43168 AS TWO INDEPENDENT FILTERS
FIGURE 10B. DATA FLOW AS DATA SAMPLE 7 IS CLOCKED INTO THE FEED FORWARD STAGE
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2 3 4 5 HSP43168 8-TAP ASYMMETRIC 8 7 6 5 INA0-9 A A 8-TAP ASYMMETRIC B B INB0-9 C0 C1 C2 C3/2 FIR B FIR A M U X OUT9-27
+
+
+
+
+
(X8 + X2)C0 + (X7 + X3)C1 + (X6 + X4)C2 + (X5 + X5)C3/2
FIGURE 11. USING HSP43168 AS TWO INDEPENDENT FILTERS
FIGURE 10C. DATA FLOW AS DATA SAMPLE 8 IS CLOCKED INTO THE FEED FORWARD STAGE FIGURE 10. DATA FLOW DIAGRAMS FOR 7-TAP SYMMETRIC FILTER
In the Data Flow Diagrams of Figure 10, the order of the data samples input in to the filter cell is shown by the numbers in the forward and backward shifting decimation paths. The output of the filter cell is given by the equation at the bottom of the block. The diagram in Figure 10A shows data sample alignment at the pre-adders for the Data/Coefficient Alignment shown in Figure 9. This dual filter application is configured by writing 110H to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Also, data reversal must be disabled by setting bit 4 of the Control Register at Address 0001H. As in the 8-tap example, only the unique coefficients need to be stored in the Coefficient Bank. These coefficients are stored in the first coefficient set for FIR A by writing C0, C1, C2, and C3 to Address 100H, 101H, 102H, and 103H respectively. To write the same filter to the first coefficient set for FIR B, the address sequence would change to 104H, 105H, 106H, and 107H. The control signals TXFR, FWRD, RVRS, ACCEN, SHFTEN, and CSEL0-4 are controlled as described in Example 1.
The operation of this configuration is better understood by comparing the Data/Coefficient Alignment in Figure 12 with the Data Flow Diagrams in Figure 13. The ALUs have been omitted from the FIR cell diagrams because data is fed to the multipliers directly from the forward and reverse decimation paths. The data samples within the FIR cell are shown by the numbers in the decimation paths.
C7 h(n) C6 C5 C4 C3 C2 C1 C0 8-TAPS
x(n)
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
FIGURE 12. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP ASYMMETRIC FILTER
Example 3: Asymmetric Filter Example
The FIR cells within the HSP43168 can each calculate 4 asymmetric taps on each clock. Thus, a single FIR cell can implement an 8-tap asymmetric filter if the HSP43168 is clocked at twice the input data rate. Similarly, if the Dual is configured as a single filter, a 16-tap asymmetric filter is realizable. Only one of the two FIR cells are used in this example for the Block Diagram shown in Figure 11. For this example, the FIR cells are configured as two 8-tap asymmetric filters which are clocked at twice the input data rate. New data is shifted into the forward and backward decimation paths every other CLK by the assertion of SHFTEN. The filter output is computed by passing data from each decimation path to the multipliers on alternating clocks. Two sets of coefficients are required, one for data on the forward decimation path, and one for data on the reverse path. The filter output is generated by accumulating the multiplier outputs for two CLKs. 13
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0 0 1 2 3 7 6 C0 C1 5 C2 4 C3 C7 C6 C5 C4 6 5 4 1 2 3
ACCUMULATOR
ACCUMULATOR
(X0)C0 + (X1)C1 + (X2)C2 + (X3)C3
(X0)C0 + (X1)C1 + (X2)C2 + (X3)C3 + (X7)C7 + (X6)C6 + (X5)C5 + (X4)C4
FIGURE 13A. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS
FIGURE 13B. SHIFTING OF DATA SAMPLE 7 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS
1 1 2 3 4 8 7 C0 C1 6 C2 5 C7 C3 C6 7
2
3
4
6
5
C5
C4
ACCUMULATOR ACCUMULATOR (X1)C0 + (X2)C1 + (X3)C2 + (X4)C3 + (X8)C7 + (X7)C6 + (X6)C5 + (X5)C4
(X1)C0 + (X2)C1 +( X3)C2 + (X4)C3
FIGURE 13C. DATA SHIFTING DISABLED, BACKWARD SHIFTING DECIMATION REGISTERS FEEDING MULTIPLIERS
FIGURE 13D. SHIFTING OF DATA SAMPLE 8 INTO FIR CELL ENABLED, FORWARD SHIFTING REGISTERS FEEDING MULTIPLIERS
FIGURE 13. DATA FLOW DIAGRAMS FOR 8-TAP ASYMMETRIC FILTER
For this application, each filter cell is configured as an odd length filter by writing 110H to the Control Register at Address 000H. Even though an even tap filter is being implemented, the filter cells must be configured as odd length to ensure proper data flow. In addition, the filters must be set to even symmetry. Also, the 4th bit at Control Address 001H must be set to disable data reversal, and TXFR must be tied low. Since an 8-tap asymmetric filter is being implemented, two sets of coefficients must be stored.
These eight coefficients could be loaded into the first two coefficient sets for FIR A by writing C0, C1, C2, C3, C7, C6, C5, and C4 to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, and 10bH respectively. The sum of products required for this 8-tap filter require dynamic control over FWRD, RVRS, ACCEN, and CSEL0-4. The relative timing of these signals is shown in Figure 14.
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0 CLK (NOTE) INA0-9 CSEL0-4 1 X0 0 X1 1 0 X6 0 X7 1 0 X8 1 0 1 2 3 13 14 15 16
ACCEN FWRD RVRS SHFTEN TXFR (TIED LOW)
The alignment of data relative to the 24 filter coefficients for a particular output is depicted graphically in Figure 16. As in previous examples, the HSP43168 implements the filtering operation by summing data samples prior to multiplication by the common coefficient. In this example an output is required every third CLK which allows 3 CLKs for computation. On each CLK, one of three sets of coefficients are used to calculate 8 of the filter taps. The Block Diagrams in Figure 17 show the data flow and accumulator output for the data/coefficient alignment in Figure 16. Proper data and coefficient alignment is achieved by asserting TXFR once every three CLKs to switch the LIFOs which are being read and written. This has the effect of feeding blocks of three samples into the backward shifting decimation path which are reversed in sample order. In addition, ACCEN is deasserted once every three clocks to allow accumulation over three CLKs. The three sets of coefficients required in the calculation of a 24-tap symmetric filter are cycled through using CSEL0-4. The timing relationship between the CSEL0-4, ACCEN, and TXFR are shown in Figure 18. To operate in this mode the Dual is configured by writing 1d2 to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Data reversal must be enabled see (Table 2). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing C2, C5, C8, C11, C1, C4, C7, C10, C0, C3, C6, and C9 to Address [100H, 101H, 102H, 103H], CSEL = 0; [108H, 109H, 10aH, 10bH], CSEL = 1; [110H, 111H, 112H, and 113H], CSEL = 2, respectively.
NOTE: CLK is 2X data rate. FIGURE 14. CONTROL TIMING FOR 8-TAP ASYMMETRIC FILTER
Example 4: Even-Tap Decimating Filter Example
The HSP43168 supports filtering applications requiring decimation to 16. In these applications the output data rate is reduced by a factor of N. As a result, N clock cycles can be used for the computation of the filter output. For example, each FIR cell can calculate 8 symmetric or 4 asymmetric taps in one clock. If the application requires decimation by two, the filter output can be calculated over two clocks thus, boosting the number of taps per FIR cell to 16 symmetric or 8 asymmetric. For this example, each FIR cell is configured as an independent 24-tap decimate x3 filter. Again, the data flow diagrams show only one of the FIR cells shown in Figure 15.
HSP43168 EVEN-TAP DECIMATING INA0-9 A A EVEN-TAP DECIMATING B B INB0-9 FIR B FIR A M U X OUT9-27
h(n) C0 C1 C4 C2 C3
C7 C5 C6
C10C11C11C10 C9 C8 C9 C8
24-TAPS C7 C6 C5 C4 C3 C2
C1 C0
x(n)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FIGURE 15. EVEN-TAP DECIMATING FILTER, 24-TAP DEC = 3
FIGURE 16. DATA/COEFFICIENT ALIGNMENT FOR 24-TAP DECIMATE BY 3 FIR FILTER
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1 05 210 21 20 19 18 543 17 16 15 876 14 13 12 11 10 9 22 21 20 19 18 17 16 15 14 13 438 7 6 11 10 9 12
+ +
C2 C5
+
C4 C7
+
C10
+
CSEL = 1
+
C8
+
C11
+
C1 CSEL = 0 ACCUMULATOR
ACCUMULATOR (X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10 +(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
FIGURE 17A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED-FORWARD STAGE
0 54
387
6 11 10
9 12 13 543 876 11 10 9 14 13 12
23
22 21 20
19 18 17
16 15 14
+
C0 C3
+
C6
+
C9
+
CSEL = 2 ACCEN ASSERTED AND ACTIVE
24
23 22 21
20 19 18
17 16 15
+
C2 C5
+
C8
+
C11
+
CSEL = 0
ACCUMULATOR
TXFR ASSERTED AND ACTIVE ACCUMULATOR
(X0 + X23)C0 + (X3 + X20)C3 + (X6 + X17)C6 + (X9 + X14)C9 + (X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10 + (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
(X5 + X24)C0 + (X8 + X21)C5 + (X11 + X18)C8 + (X14 + X15)C11
FIGURE 17C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 17. DATA FLOW DIAGRAMS FOR 24-TAP DECIMATED BY 3 FIR FILTER
0 CLK
1
2
3
4
5
21
22
23
Example 5: Odd-Tap Decimating Symmetric Filter
This example highlights the use of the HSP43168 as two independent, 23-tap, symmetric, decimate by 3 filters. In this example, the operational differences in the control signals and data reversal structure may be compared to the previously discussed even-tap decimating filter. Figure 19 shows two FIR cells. The data flow in this example uses only one of the FIR cells.
HSP43168 ODD-TAP DECIMATING
INA0-9
0
1
2
3
4
5
21
22
23
CSEL0-4
0
1
2
0
1
2
0
1
2
ACCEN FWRD RVRS INA0-9 SHIFTEN A A ODD-TAP DECIMATING TXFR B B INB0-9 FIR B FIR A M U X OUT9-27
Tied low. FIGURE 18. CONTROL SIGNAL TIMING FOR 24-TAP DECIMATE X3 FILTER FIGURE 19. USING HSP43168 AS TWO INDEPENDENT FILTERS
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As in the 24-tap example, an output is required every third CLK which allows 3 CLKs for computation. On each CLK, one of three sets of coefficients are used to calculate the filter taps. Since this is an odd length filter, the center coefficient must be scaled by 1/2 to compensate for the summation of the same data sample from the forward and backward shifting decimation paths. The Block Diagrams in Figure 20 show the data flow, and the accumulator output for the data coefficient alignment is shown in Figure 21. Proper data and coefficient alignment is achieved by asserting TXFR once every three CLKs to switch the LIFOs which are being read and written. In the odd-tap mode, TXFR is internally delayed by one clock cycle with respect to ACCEN so that the convolutional sum will be computed correctly. For odd length filters, data prior to the last register in the forward decimation path is routed to the feedback circuitry. As a result, TXFR should be asserted one cycle prior to the input data samples which align with the center tap. The timing relationship between the CSEL0-5, ACCEN, and TXFR are shown in Figure 22.
216 321 654 987 12 11 10 22 21 20 19 18 17 16 15 14 13 12 21 20 19
549
8 7 12
11 10 13
18 17 16
15 14 13
+ +
C2 C5
+
C4 C7
+
C10
+
CSEL = 1
+
C8
+
C11/2
+
C1 CSEL = 0 ACCUMULATOR
ACCUMULATOR (X2 + X22)C1 + (X5 + X19)C4 + (X8 + X16)C7 + (X11 + X13)C10 + (X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
(X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
FIGURE 20A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED-FORWARD STAGE TXFR TAKES AFFECT ON THIS CLOCK CYCLE
FIGURE 20B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED-FORWARD STAGE
165
498
7 12 11
10 13 14
654
987
12 11 10
15 14 13
23
22 21 20
19 18 17
16 15 14
24
23 22 21
20 19 18
17 16 15
+
C0 C3
+
C6
+
C9
+
CSEL = 2 ACCEN ASSERTED AND ACTIVE TXFR ASSERTED
+
C2 C5
+
C8
+
C11/2
+
CSEL = 0
ACCUMULATOR
ACCUMULATOR
(X1 + X23)C0 + (X4 + X20)C3 + (X7 + X17)C6 + (X14 + X10)C9 + (X2 + X22)C1 + (X5 + X19)C4 + (X8 + X16)C7 + (X11 + X13)C10 + (X3 + X21)C2 + (X6 + X18)C5 + (X9 + X15)C8 + (X12 + X12)C11/2
(X6 + X24)C2 + (X9 + X21)C5 + (X12 + X18)C8 + (X15 + X15)C11/2
FIGURE 20C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 20D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED-FORWARD STAGE TXFR TAKES AFFECT ON THIS CLOCK CYCLE
FIGURE 20. DATA FLOW DIAGRAMS FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER
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C11 C10 C10 C9 C9
Example 6. Dual Decimation Example
23-TAPS C8 C7 C6 C5 C4
h(n) C1 C2 C3 C4 C5
C6
C7 C8
C3
C0
C2 C1
C0
x(n)
The purpose of this example is to give an overview of one of the more complex applications of the HSP43168. The input is two data streams (A) and (B) samples. Figure 23 shows the upper level block diagram of the system being implemented. The decimation rate was set to N. N-1 is loaded into the decimation factor in Control Word 000H.
FS
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B3, B2, B1, B0 INB0-9 HSP43168 INA0-9 DECIMATE BY N
2FS /(N+1) OUT9-27 BOUT1 AOUT1 BOUT0 AOUT0
FIGURE 21. DATA/COEFFICIENT ALIGNMENT FOR 23-TAP DECIMATE BY 3 SYMMETRIC FILTER
A3, A2, A1, A0
0 CLK 0 1
1
2
3
4
5
20
21
22
FIGURE 23. MULTIPLEXED DECIMATION BLOCK DIAGRAM
INA0-9
2
3
4
5
21
22
23
CSEL0-4
0
1
2
0
1
2
0
1
2
ACCEN FWRD RVRS SHIFTEN TXFR
To demonstrate the muxed decimation, lets suppose that the application requires filter A to be configured as an even-decimate-by-3 filter and filter B to be configured as a odd-decimate-by-3 filter. The output data is made of the two decimated data streams multiplexed together and has a data rate equal to 2x the input sampling rate divided by the decimation factor. Figure 24 shows the data/coefficient alignment for FIR A and FIR B. To operate in this mode, Control Word 000H must be written with a 0x152. Data reversal must be enabled by setting bit 4 of Control Word 001H = 0. The filter set selected by CSEL0-4 = 0 should be loaded by writing C2, C5, C8, C11, D2, D5, D8, and (D11)/ 2 into 100H, 101H, 102H, 103H, 104H, 105H, 106H, and 107H. The filter set selected by CSEL0-4 = 1 should be loaded by writing C1, C4, C7, C10, D1, D4, D7, and D10 into 108H, 109H, 10aH, 10bH, 10cH, 10dH, 10eH, and 10fH. The filter set selected by CSEL0-4 = 2 should be loaded by writing C0, C3, C6, C9, D0, D3, D6, and D9 into 110H, 111H, 112H, 113H, 114H, 115H, 116H, and 117H.
Tied low. FIGURE 22. CONTROL SIGNAL TIMING FOR 23-TAP SYMMETRIC FILTER
To operate in this mode, the Dual is configured by writing 112H to Address 000H via the microprocessor interface, CIN0-9, A0-8, and WR. Data reversal must be enabled (see Table 2). The 12 unique coefficients for this example are stored as three sets of coefficients for either FIR cell. For FIR A, the coefficients are loaded into the Coefficient Bank by writing [C2, C5, C8, (C11)/ 2], CSEL = 0; [C1, C4, C7, C10], CSEL = 1; [C0, C3, C6, and C9], CSEL = 2; to address 100H, 101H, 102H, 103H, 108H, 109H, 10aH, 10bH, 110H, 111H, 112H, and 113H, respectively.
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D11 D10 D10
h2(n) D0 D1 D2 D3
D4
D5
D6
D7
D8
D9
D9
FIRB
D8 D7 D6 D5 D4 D3
23-TAPS
D2
D1
D0
Figure 25 shows the Timing Diagram required to obtained the multiplexed/decimated output. The output of the two filters are provided at by selecting the odd-decimation filter first, then the even-decimation second using MUX0-1. Figure 26 shows the Data Flow Diagram for the multiplexed decimation example.
0 CLK 1 2 3 4 5 20 21 22
B(n)
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
76543210 INA0-9 CSEL0-4 0 1 2 3 4 5 20 21 22
h1(n) C0 C1 C2 C3 C4
C5 C6
C7 C8
C11 C11 C10C9 C9C10
C8 C7
FIRA
C6 C5 C4
24-TAPS
0
1
2
0
1
2
2
0
1
C3 C2
C1 C0
ACCEN MUX0-1 11 10 11 11 10 11
A(n)
TXFR
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIGURE 24. DATA/COEFFICIENT ALIGNMENT FOR MULTIPLEXED DECIMATION EXAMPLE
FIGURE 25. TIMING DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE
FIR B
321 B DATA STREAM 21 20 19 18 17 16 15 14 13 12 654 987 12 11 10 22
FIR B
216 549 8 7 12 11 10 13 21 20 19 18 17 16 15 14 13
+ +
D2 D5
+
D4 D7
+
D10
+
CSEL = 1
+
D8
+
D11/2
+
D1 CSEL = 0
ACCUMULATOR ACCUMULATOR (X2 + X22)D1 + (X5 + X19)D4 + (X8 + X16)D7 + (X11 + X13)D10 + (X3 + X21)D2 + (X6 + X18)D5 + (X9 + X15)D8 + (X12 + X12)D11/2
(X3 + X21)D2 + (X6 + X18)D5 + (X9 + X15)D8 + (X12 + X12)D11/2
FIR A
A DATA STREAM 21 210 543 876 11 10 9 1 05 438 7 6 11
FIR A
10 9 12
20 19 18
17 16 15
14 13 12
22
21 20 19
18 17 16
15 14 13
+
C2 C5
+
C8
+
C11
+
CSEL = 0 C1
+
C4
+
C7
+
C10
+
CSEL = 1
ACCUMULATOR
ACCUMULATOR
(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
(X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10 +(X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
FIGURE 26A. COMPUTATIONAL FLOW AS DATA SAMPLE 21 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 26B. COMPUTATIONAL FLOW AS DATA SAMPLE 22 IS CLOCKED INTO THE FEED-FORWARD STAGE
19
FN2808.12 July 27, 2009
HSP43168
FIR B
165 498 7 12 11 10 13 14 23 22 21 20 19 18 17 16 15 14 24 23 22 21 20 19 18 17 16 15 654 987 12 11 10
FIR B
15 14 13
+
D0 D3
+
D6
+
D9
+
CSEL = 2 D2
+
D5
+
D8
+
D11/2
+
CSEL = 0
ACCUMULATOR
OUTPUT OF B IS SENT TO OUT9-27
ACCUMULATOR
(X1 + X23)D0 + (X4 + X20)D3 + (X7 + X17)D6 + (X14 + X10)D9 + (X2 + X22)D1 + (X5 + X19)D4 + (X8 + X16)D7 + (X11 + X13)D10 + (X3 + X21)D2 + (X6 + X18)D5 + (X9 + X15)D8 + (X12 + X12)D11/2
(X6 + X24)D2 + (X9 + X21)D5 + (X12 + X18)D8 + (X15 + X15)D11/2
FIR A
0 54 387 6 11 10 9 12 13 23 22 21 20 19 18 17 16 15 14 24 23 22 21 20 19 18 17 16 15 543 876 11 10 9
FIR A
14 13 12
+
C0 C3
+
C6
+
C9
+
CSEL = 2 C2
+
C5
+
C8
+
C11
+
CSEL = 0
ACCUMULATOR
ACCUMULATOR
OUTPUT OF A IS SENT TO OUT9-27
(X0 + X23)C0 + (X3 + X20)C3 + (X6 + X17)C6 + (X9 + X14)C9 + (X1 + X22)C1 + (X4 + X19)C4 + (X7 + X16)C7 + (X10 + X13)C10 + (X2 + X21)C2 + (X5 + X18)C5 + (X8 + X15)C8 + (X11 + X12)C11
(X5+X24)C0+(X8+X21)C5+(X11+X18)C8+(X14+X15)C11
FIGURE 26C. COMPUTATIONAL FLOW AS DATA SAMPLE 23 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 26D. COMPUTATIONAL FLOW AS DATA SAMPLE 24 IS CLOCKED INTO THE FEED-FORWARD STAGE
FIGURE 26. DATA FLOW DIAGRAM FOR MULTIPLEXED DECIMATION EXAMPLE
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FN2808.12 July 27, 2009
HSP43168
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Input, Output or I/O Voltage . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 2) . . . . . . . . . . . . . JA (C/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Maximum Junction Temperature MQFP and PLCC Packages . . . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 5% Temperature Range, Commercial . . . . . . . . . . . . . . . . 0C to +70C Temperature Range, Industrial. . . . . . . . . . . . . . . . . .-40C to +85C
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V Number of Transistors or Gates. . . . . . . . . . . . . . . . . . . . . . . . 32529
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty
NOTE: 2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379.
DC Electrical Specifications
PARAMETER Power Supply Current Standby Power Supply Current Input Leakage Current Output Leakage Current Logical One Input Voltage Logical Zero Input Voltage Logical One Output Voltage Logical Zero Output Voltage Clock Input High Clock Input Low Input Capacitance Output Capacitance NOTES: 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 4. Power Supply current is proportional to operating frequency. Typical rating for ICCOP is 11mA/MHz. 5. Output load per test load circuit and CL = 40pF. 6. Maximum junction temperature must be considered when operating part at high clock frequencies. SYMBOL ICCOP ICCSB II IO VIH VIL VOH VOL VIHC VILC CIN COUT TEST CONDITIONS VCC = Max (Notes 4, 5, 6) CLK Frequency 33MHz VCC = Max, Outputs Not Loaded VCC = Max, Input = 0V or VCC VCC = Max, Input = 0V or VCC VCC = Max VCC = Min IOH = -400A, VCC = Min IOL = 2mA, VCC = Min VCC = Max VCC = Min CLK Frequency 1MHz All measurements referenced to GND. TA = +25C, (Note 3) MIN -10 -10 2.0 2.6 3.0 MAX 363 500 10 10 0.8 0.4 0.8 12 12 UNITS mA A A A V V V V V V pF pF
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FN2808.12 July 27, 2009
HSP43168
AC Electrical Specifications
VCC = +4.75V to +5.25V, TA = 0C to +70C Commercial, TA = -40C to +85C Industrial (Note 7) -33 (33MHz) PARAMETER CLK Period CLK High CLK Low WR Period WR High WR Low Setup Time A0-8 to WR Going Low Hold Time A0-8 from WR Going High Setup Time CIN0-9 to WR Going High Hold Time CIN0-9 from WR Going High Setup Time WR Low to CLK Low Setup Time CIN0-9 to CLK Low Setup Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High Hold Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High CLK to Output Delay OUT0-27 Output Enable Time Output Disable Time Output Rise, Fall Time NOTES: 7. AC tests performed with CL = 40pF, IOL = 2mA, and IOH = -400A. Input reference level CLK = 2.0V. Input reference level for all other inputs is 1.5V. Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V, VILC = 0V. 8. Setup time requirement for loading of data on CIN0-9 to guarantee recognition on the following clock. 9. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 10. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 11. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL tCP tCH tCL tWP tWH tWL tAWS tAWH tCWS tCWH tWLCL tCVCL tECS (Note 8) (Note 8) NOTES -40 (40.8MHz) -45 (45MHz)
MIN MAX MIN MAX MIN MAX (Note 11) (Note 11) (Note 11) (Note 11) (Note 11) (Note 11) UNITS 30 12 12 30 12 12 10 0 12 1 5 7 15 24.5 10 10 24.5 10 10 8 0 11 1 4 7 13 22 8 8 22 10 10 8 0 10 1 3 7 12 ns ns ns ns ns ns ns ns ns ns ns ns ns
tECH
0
-
0
-
0
-
ns
tDO tOE tOD tRF (Note 9) (Note 9)
-
14 12 12 6
-
13 12 12 6
-
12 12 12 6
ns ns ns ns
AC Test Load Circuit
DUT
S1
CL (NOTE)
Note: Test head capacitance.
SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH 1.5V IOL
EQUIVALENT CIRCUIT
22
FN2808.12 July 27, 2009
HSP43168 Waveforms
tCP tCH CLK tCL
CSEL0 - 4, MUX0 - 1 SHFTEN, FWRD RVRS, TXFR INA0 - 9, INB0 - 9, ACCEN
tECS
tECH
tDO
OUT0 - 27
tWLCL tWP tWL WR tWH
tAWS A0 - 8
tAWH
tCWS CIN0 - 9
tCWH
tCVCL
OEL, OEH
1.5V tOE
1.5V tOD 1.7V 1.3V
OUT0 - 27 HIGH IMPEDANCE
HIGH IMPEDANCE
FIGURE 27. OUTPUT ENABLE, DISABLE TIMING
2.0V 0.8V tRF
2.0V 0.8V tRF
FIGURE 28. OUTPUT RISE AND FALL TIMES
23
FN2808.12 July 27, 2009
HSP43168 Metric Plastic Quad Flatpack Packages (MQFP)
D D1 -D-
Q100.14x20 (JEDEC MS-022GC-1 ISSUE B)
100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE INCHES SYMBOL A A1 MIN 0.010 0.101 0.009 0.009 0.908 0.782 0.673 0.547 0.029 100 0.026 BSC 30 20 MAX 0.134 0.113 0.015 0.013 0.918 0.792 0.681 0.555 0.040 MILLIMETERS MIN 0.25 2.57 0.22 0.22 23.08 19.88 17.10 13.90 0.73 100 0.65 BSC 30 20 MAX 3.40 2.87 0.38 0.33 23.32 20.12 17.30 14.10 1.03 NOTES 6 3 4, 5 3 4, 5 7 Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and tolerances per ANSI Y14.5M-1982.
b1 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING 0.13/0.23 0.005/0.009
-AE E1
-B-
A2 b b1 D D1 E
e
PIN 1 SEATING A PLANE 0.076 0.003 12o-16o 0.40 0.016 MIN 0o MIN 0o-7o A2 A1 0.20 M 0.008 C A-B S -CDS b
E1 L N e ND NE
-H-
3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. "N" is the number of terminal positions.
L
12o-16o
24
FN2808.12 July 27, 2009
HSP43168 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C
N84.1.15 (JEDEC MS-018AF ISSUE A)
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A MIN 0.165 0.090 1.185 1.150 0.541 1.185 1.150 0.541 84 MAX 0.180 0.120 1.195 1.158 0.569 1.195 1.158 0.569 MILLIMETERS MIN 4.20 2.29 30.10 29.21 13.75 30.10 29.21 13.75 84 MAX 4.57 3.04 30.35 29.41 14.45 30.35 29.41 14.45 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 E1 E C L
A1 D D1
D2/E2 VIEW "A"
D2 E E1
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
E2 N
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN VIEW "A" TYP.
0.025 (0.64) MIN
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 25
FN2808.12 July 27, 2009

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